module 	main_ctrl_u(
    input				    clk,
    input				    rst_n,
    input			    	ena,
    input                   branch_taken,
    input	   [63:0]   	PC_branch,
    output reg [3 :0]       flush,
    output reg [3 :0]       pip_ena,
    output reg [63:0]		PC_new,
    output reg              branch_taken_i
);
    always@(posedge clk or negedge rst_n)  begin
            if(!rst_n)begin
                pip_ena<=5'd0;                
            end
            else begin
                pip_ena<={pip_ena[3:0],ena};
            end
    end
    always@(posedge clk or negedge rst_n)  begin
            if(!rst_n)begin
                branch_taken_i<=1'b0;
            end
            else begin
                branch_taken_i<=branch_taken;
            end
    end
    always@(posedge clk or negedge rst_n)  begin
            if(!rst_n)begin
                PC_new<=64'd0;
            end
            else begin
                PC_new<=PC_branch;
            end
    end
    always@(posedge clk or negedge rst_n)  begin
            if(!rst_n)begin
                flush<=4'd0;
            end
            else begin
                flush<=branch_taken_i?4'b0011:4'b0000;
            end
    end
endmodule